I. Field of the Invention
The present invention relates to a semiconductor device and, more particularly, to a semiconductor device of improved integration which is suitable to be used as an MOS transistor integrated circuit.
II. Description of the Prior Art
Recent improvements in integration in MOS transistor integrated circuits are immense. The main factor which supported such improvements in high integration is the technological development for reducing the element size. Multi-wiring technique has also contributed to these improvements. For example, it has been proposed to eliminate the aluminum wiring from the memory cell using a buried J-FET and to reduce the memory cell area so as to attain a high integration density CMOS IC as described in C. Minato et al, "Buried J-FET Powered Static RAM Cell" Digest of Tech. Papers, The 11th Conf. on Solid State Devices, Tokyo, 1979.
FIG. 1 is a cross sectional view of a conventional enhancement-depletion (E/D) type inverter circuit device formed by an enhancement type MOS transistor and a depletion type MOS transistor. As shown in this figure, n-type semiconductor regions 2, 3 and 4 are formed in a p-type semiconductor substrate 1. A gate electrode 6 is formed on an insulation layer 5, above the area of the semiconductor substrate 1 between the semiconductor regions 2 and 3. Similarly, a gate electrode 7 is formed on the insulation layer 5 above the area of the semiconductor substrate 1 between the semiconductor regions 3 and 4.
A donor impurity is ion-implanted in the surface area (channel portion) of the semiconductor substrate 1 between the semiconductor regions 2 and 3 so as to make the threshold voltage negative (e.g., -2 V), thus providing a depletion type MOS transistor having the semiconductor region 2 as a drain region and the semiconductor region 3 as a source region. An acceptor impurity is ion-implanted in the surface area (channel portion) of the semiconductor substrate 1 between the semiconductor regions 3 and 4 so as to make the threshold voltage positive (e.g., +1 V), thus providing an enhancement type MOS transistor having the semiconductor region 3 as a drain region and the semiconductor region 4 as a source region.
According to this construction, the drain region 2 of the depletion type MOS transistor is connected to a power source voltage terminal VD, and the source region 3 and the gate electrode 6 are commonly connected to the output terminal VOUT. The gate electrode 7 of the enhancement type MOS transistor is connected to an input terminal VIN, and the source region 4 is connected to a ground terminal VS1. The semiconductor substrate is connected to a ground terminal VS2. An E/D inverter circuit is thus formed.
As may be seen from the above construction, with a semiconductor device comprising a conventional E/D type inverter circuit device, a total of four kinds of wirings are required on the same surface of a substrate, i.e., the input terminal connecting wiring, the output terminal connecting wiring, the power source connecting wiring, and the grounding wiring, and the freedom of design of the wirings is limited. As a result, high integration density of the MOS IC has been difficult to achieve and the fabrication process has been complex.
It is, therefore, the primary object of the present invention to provide a semiconductor device which may be fabricated in a relatively simple manner and which may attain a high integration density.